MC68HC05PV8 Datasheet, PDF (66/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
4.2 Introduction
The MCU can be interrupted in different ways:
1. Nonmaskable Software Interrupt Instruction (SWI)
2. External Asynchronous Interrupt (IRQ)
3. External Asynchronous Interrupt on Port A
4. External Asynchronous Interrupt on Port C
5. Internal 8-bit Timer Interrupt (CTIMER)
6. Internal 16-bit Timer1 Interrupt (TIMER)
7. Low Voltage Interrupt
8. Port C5 & C6 Short Circuit Interrupt
9. High Voltage Interrupt
10. High Temperature Interrupt
4.3 CPU Interrupt Processing
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I-bit) to prevent additional interrupts.
Unlike RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete.
If interrupts are not masked (I-bit in the CCR is clear) and the
corresponding interrupt enable bit is set, then the processor proceeds
with interrupt processing. Otherwise, the next instruction is fetched and
executed. If an interrupt occurs, the processor completes the current
instruction, then stacks the current CPU register states, sets the I-bit to
inhibit further interrupts, and finally checks the pending hardware
interrupts. If more than one interrupt is pending following the stacking
operation, the interrupt with the highest vector location shown in Table
4-1 is serviced first. The SWI is executed the same as any other
instruction, regardless of the I-bit state.
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
Interrupts
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