MC68HC05PV8 Datasheet, PDF (88/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
6.3 User mode
Intended mode of operation for executing user firmware.
6.4 Monitor Mode
Used for programming the on-chip Program or Data EEPROM
(68HC805PV8) and Data EEPROM (68HC05PV8) if desired.
6.5 Low Power Modes
The MC68HC(8)05PV8/A is capable of running in one of several
low-power operational modes. The WAIT and STOP instructions provide
two modes that reduce the power required for the MCU by stopping
various internal clocks and/or the on-chip oscillator. The flows of the
STOP and WAIT modes are shown in Figure 6-2.
6.5.1 STOP Mode
The STOP instruction places the MCU in its lowest power consumption
mode. In STOP mode, the internal oscillator is turned off, halting all
internal processing, including timer (and COP watchdog timer)
operation.
During STOP mode, the core timer interrupt flags and interrupt enable
bits of the CTCSR register are cleared by internal hardware to remove
any pending timer interrupt requests and to disable any further timer
interrupts. The timer pre-scaler is also cleared. The I bit in the CCR is
cleared to enable external interrupts. All other registers, including the
remaining bits in the CTCSR, and memory remain unaltered. All
input/output lines remain unchanged. The processor can be brought out
of the STOP mode only by an external interrupt or RESET.
The STOP instruction can be disabled by a mask option. When disabled,
the STOP instruction causes a system reset.
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
Operating Modes
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