MC68HC05PV8 Datasheet, PDF (120/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
RTOF – Reset TOF
This bit always reads 0. Setting this bit clears the timer overflow flag
(TOF). Clearing this bit has no effect.
RRTIF – Reset RTIF
This bit always reads 0. Setting this bit clears the real time interrupt
flag (RTIF). Clearing this bit has no effect.
RT1, RT0 – Real Time Interrupt Rate Select
These two bits select one of four taps from the real time interrupt
circuit. Table 8-1 shows the available interrupt rates with several f_op
values. Reset sets these RT0 and RT1, selecting the lowest periodic
rate and therefore the maximum time in which to alter these bits if
necessary. Care should be taken when altering RT0 and RT1 if the
time-out period is imminent or uncertain. If the selected tap is modified
during a cycle in which the counter is switching an RTIF could be
missed or an additional one could be generated. To avoid problems
the COP should be cleared before changing RTI taps.
RT1:RT0
00
01
10
11
500 kHz
32.768ms
65.536ms
131.072ms
262.144ms
Table 8-1 RTI Rates
RTI Rates at Bus Frequency f_OP specified:
1.000 MHz 2.000 MHz 2.4576 MHz
16.384ms
8.192ms
6.667ms
32.768ms
16.384ms
13.333ms
65.536ms
32.768ms
26.667ms
131.072ms
65.536ms
53.333ms
RATIO
2¹⁴/f_op
2¹⁵/f_op
2¹⁶/f_op
2¹⁷/f_op
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
Core Timer
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