MC68HC05PV8 Datasheet, PDF (97/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
Input/Output Ports
Port A
7.4.4 Port A Configuration Register
$0020 Bit 7
6
5
4
3
2
1
Read:
VRHEN
Write:
PUHEN
EDGEH
PAHIE
PULEN EDGEL
PALIE
Reset: 0
0
0
0
0
0
0
Figure 7-2 Port A Configuration Register (PACFG)
Bit 0
VRLEN
0
VRHEN – Enable A/D High Reference Channel
Those bits connect the PA7 pin with the A/D high reference channel.
1 = A/D high reference channel connected to external VREFH.
0 = A/D high reference channel connected to internal voltage
supply.
PUHEN – PA4–7 Pull-Up Resistor Enable Higher Nibble
This bit disables/enables the pull-up resistors of the PA4–7 pins.
1 = PA4–7 pull-up resistors disabled
0 = PA4–7 pull-up resistors enabled
EDGEH – PA4–7 Interrupt Edge Higher Nibble
This bit selects the trigger edges of the interrupt lines PA4–7.
1 = Rising edge sensitive
0 = Falling edge sensitive
PAHIE – PA4–7 Interrupt Enable Higher Nibble
This bit disables/enables the PA4–7 pins as an interrupt group.
1 = PA4–7 interrupt enabled
0 = PA4–7 interrupt disabled
PULEN – PA0–3 Pull-Up Resistor Enable Lower Nibble
This bits disables/enables the pull-up resistors of the PA0–3 pins.
1 = PA0–3 pull-up resistors disabled
0 = PA0–3 pull-up resistors enabled
EDGEL – PA0–3 Interrupt Edge Lower Nibble
This bit selects the trigger edges of the interrupt lines PA0–3.
1 = Rising edge sensitive
0 = Falling edge sensitive
MC68HC(8)05PV8/A — Rev. 1.9
Input/Output Ports
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Technical Data