MC68HC05PV8 Datasheet, PDF (83/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
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Computer Operating Properly Reset (COPR)
5.7.3 COP During STOP Mode
When the STOP enable mask option is selected, STOP mode disables
the oscillator circuit and thereby turns the clock off for the entire device.
The COP counter is reset when STOP mode is entered. If a reset is used
to exit STOP mode, the COP counter is held in reset during the 4064
cycles of start up delay. If any operable interrupt is used to exit STOP
mode, the COP counter is not reset during the 4064 cycle start-up delay
and has the number of cycles already counted when control is returned
to the program.
5.7.4 COP Watchdog Timer Considerations
The COP watchdog timer is active in user mode if enabled by the
COPEN bit in the mask option register. If the COP watchdog timer is
selected, any execution of the STOP instruction (either intentional or
inadvertent due to the CPU being disturbed) causes the oscillator to halt
and prevent the COP watchdog timer from timing out. Therefore, it is
recommended that the STOP instruction should be disabled if the COP
watchdog timer is enabled.
If the COP watchdog timer is selected, the COP resets the MCU when it
times out. Therefore, it is recommended that the COP watchdog be
disabled for a system that must use the WAIT mode for periods longer
than the COP time-out period.
5.7.5 COP Register
The COP register is shared with the MSB of the contact sense interrupt
vector as shown in Figure 5-3. Reading this location returns whatever
user data has been programmed at this location. Writing a 0 to the
COPR bit in this location clears the COP watchdog timer.
MC68HC(8)05PV8/A — Rev. 1.9
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Technical Data