MC68HC05PV8 Datasheet, PDF (80/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
5.5 Internal Resets
The eight internally generated resets are the initial power-on reset
function, the COP watchdog timer reset, the illegal address detector,
clock-monitor, the high temperature reset, high voltage reset,
low-voltage reset, and the disabled STOP instruction.
When forcing RESET externally to V_DD, all temperature, voltage and
clock-monitor dependent reset sources are disabled. In this case, the
internal pull-down device tries to pull down the pin until the next
recognized internal reset, which leads to some power-consumption.
INTERNAL
PULLUP
RESET
PIN
VDD
INTERNAL
RESET
LOGIC
INTERNAL
RESETS
5.6 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and is not
able to detect a drop in the power supply voltage (brown-out). There is
an oscillator stabilization delay of t_PORLafter the oscillator becomes
active. See Figure 5-2 for details. T_PORLis 4064 internal processor clock
cycles.
The POR generates the RST signal which resets the CPU. If any other
reset function is active at the end of this t_PORL delay, the RST signal
remains in the reset condition until the other reset condition(s) ends.
POR activates the RESET pin pull-down device connected to the pin.
VDD must drop below V_POR in order for the internal POR circuit to detect
the next rise of V_DD.
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
Resets
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