MC68HC05PV8 Datasheet, PDF (152/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
11.4.3 PWM Period Register
The PWM system has an 8-bit period register that holds the PWM
period. The frame frequency of the PWM system is defined as
f_frame=f_PWM/(PWMPR + 1).
This register can be written at any time. The period of the output changes
after the current cycle.
$002C Bit 7
6
5
4
3
2
1
Bit 0
Read:
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 11-6 PWM Period Register (PWMPR)
11.5 PWM During WAIT Mode
The PWM continues normal operation during WAIT mode. To decrease
power consumption during WAIT it is recommended to shut off the PWM
by clearing the PWMON bit if the PWM system is not used.
11.6 PWM During STOP Mode
In STOP mode the oscillator is stopped, causing the PWM to cease
functioning. Any signal in process is aborted in whatever phase the
signal happens to be in.
11.7 PWM During Reset
Upon reset the PWMON and PRA3–0 bits in the PWM control register
are cleared, the data register is written with $00 and the polarity bit is
reset. This in effect disables the PWM system and sets the output driving
high. The user should write to the data register, the period register, the
polarity bit and the clock rate bits prior to enabling the PWM system (i.e.
prior to setting PWMON). This prevents an erroneous duty cycle from
being driven.
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
Pulse Width Modulator
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