MC68HC05PV8 Datasheet, PDF (117/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
Technical Data — MC68HC(8)05PV8/A
8.1 Contents
Section 8. Core Timer
8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
8.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
8.3.1 Core Timer Status & Control Register (CTSCR) . . . . . . . .119
8.3.2 Computer Operating Properly (COP) Watchdog Reset. . . 121
8.3.3 Core Timer Counter Register (CTCR). . . . . . . . . . . . . . . . 121
8.4 Core Timer During WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
8.5 Core Timer During STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
8.2 Introduction
The core timer for this device is a 15-stage multi-functional ripple
counter. The features include timer over flow, power-on reset (POR),
real time interrupt (RTI), and COP watchdog timer.
As seen in Figure 8-1, the timer is driven by the output of the clock select
circuit followed by a fixed divide by four pre-scaler. This signal drives an
8-bit ripple counter. The value of this 8-bit ripple counter can be read by
the CPU at any time by accessing the timer counter register (TCR) at
address $09. A timer overflow function is implemented on the last stage
of this counter, giving a possible interrupt at the rate of f_op/1024. Two
additional stages produce the POR function after 4064 clks (if selected).
The timer counter bypass circuitry (available only in test mode) is at this
point in the timer chain. This circuit is followed by two more stages, with
the resulting clock (f_op/16384) driving the real time interrupt circuit. The
RTI circuit consists of three divider stages with a 1 of 4 selector. The
output of the RTI circuit is further divided by eight to drive the mask
optional COP watchdog timer circuit. The RTI rate selector bits, and the
MC68HC(8)05PV8/A — Rev. 1.9
Core Timer
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Technical Data