MC68HC05PV8 Datasheet, PDF (169/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
Technical Data — MC68HC(8)05PV8/A
15.1 Contents
Section 15. Fast Parallel Interface
15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
15.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
15.3.1 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 171
15.2 Introduction
The MC68HC(8)05PV8/A includes a fast parallel interface to access
external peripheral components as fast as internal ones. The external
address space ranges from $0030 to $003F and all 68HC05 instructions
can be applied to this memory. Since the data path is only 4-bits wide
either the lines PA7–PA4 or the corresponding data bits in the port A
data register are read depending on the state of the DDRA7–DDRA4
bits.
15.3 Description
If this interface is enabled by setting the FPIE bit in the system control
register PA0–3 and PB0–3 lines provide a 4 bit address, multiplexed with
4 bit wide data and timing control lines.
The interface uses the lower port A lines (PA0–3) to provide a 4 bit
address multiplexed with 4 bit wide data. The timing is controlled by port
B lines.
MC68HC(8)05PV8/A — Rev. 1.9
Fast Parallel Interface
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Technical Data