MC68HC05PV8 Datasheet, PDF (158/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
13.3 EEPROM Control Register (EEPCR)
$000C
Read:
Write:
Reset:
Bit 7
6
0
0
5
4
3
2
1
0
EEOSC EER1 EER0 EELAT
0
0
0
0
0
0
0
Figure 13-1 EEPROM Control Register (EEPCR)
Bit 0
EEPGM
0
EEOSC – EEPROM RC Oscillator Control
When this bit is set, the EEPROM section uses the internal RC
oscillator instead of the CPU clock. The user must wait a time t_RCON
after setting the EEOSC bit to allow the RC oscillator to stabilize.
EEOSC is readable and writable. It should be set by the user when
the internal bus frequency falls below 1.5 MHz. Reset clears this bit.
EER1, EER0 – Erase Select Bits
EER1 and EER0 form a 2-bit field that is used to select one of three
erase modes: byte, block, or bulk erase. Table 13-1 shows the modes
selected for each bit configuration. These bits are readable and
writable and are cleared by reset.
In byte erase mode, only the selected byte is erased. In block mode,
a 128-byte block of EEPROM is erased. The EEPROM memory
space is divided into two 64-byte blocks ($0180–$01BF,
$01C0–$01FF) and performing a block erase on any address within
a block will erase the entire block. In bulk erase mode, the entire 128
byte EEPROM section is erased.
A block protect function applies on block2 of the EEPROM memory
space. See 13.4 EEPROM Options Register (EEOPR) for more
details.
Table 13-1 Erase Mode Select
EER1
0
0
1
1
EER0
0
1
0
1
MODE
No erase
Byte erase
Block erase (block1 or block2)
Bulk erase (block1 & block2)
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
EEPROM
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