MC68HC05PV8 Datasheet, PDF (188/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
16.14 Fast Peripheral Interface Timing
(V_DD = 5.0Vdc ±10%, V_SS = 0Vdc, T_J = –40°C to +125°C, unless otherwise noted)
Characteristic
Symbol Min
Max
Unit
Comment
DEN/AS Rise and Fall Time
Pulse Width AS, DEN high
t_R
-
25
ns
t_F
-
25
ns
PW
210
-
ns
See ➀
See ➁
Address, CS, RW setup time
Address, CS, RW hold time
Read data setup time
Read data hold time
Write data setup time
Write data hold time
t_AS
49
-
ns
t_AH
22
-
ns
t_DSR
100
-
ns
t_DHR
50
-
ns
t_DSW
30
-
ns
t_DHW
30
-
ns
See ➂
See ➃
See ➄
See ➅
See ➆
See ➇
NOTES:
1. The first cycle denotes a read, the second a write cycle.
2. Unlike in the HC11 AS and DEN occur only when accessing the external memory if not
enabled continuously.
3. OSC1/OSC2 input clock other than 50% duty cycle affect bus performance.
4. All timing is shown with respect to 20% V_DD and 70% V_DD, unless otherwise noted.
1
PB0/AS
PB2/DEN
PB3/CS
PB1/RW
PA3:0
Technical Data
1
2
3
4
1
1
5
6
7
8
R/W
R/W
A3:0
D3:0
A3:0
D3:0
Figure 16-4 Timing definition
MC68HC(8)05PV8/A — Rev. 1.9
Electrical Specifications
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