MC68HC05PV8 Datasheet, PDF (63/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
CPU and Instruction Set
Instruction Set Summary
Table 3-6 Instruction Set Summary (Continued)
Source
Form
Operation
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte for Negative or Zero
Description
(M) – $00
Effect on
CCR
H I NZC
DIR 3D ^dd 4
INH 4D
3
— — ↕ ↕ — INH 5D
3
IX1 6D _ff 5
IX 7D
4
TXA
Transfer Index Register to Accumulator
A ← (X)
— — — — — INH 9F
2
WAIT
Stop CPU Clock and Enable Interrupts
—
0
◊
—
——
INH
8F
2
A Accumulatoropr
C Carry/borrow flagPC
CCRCondition code registerPCH
ddDirect address of operandPCL
dd rrDirect address of operand and relative offset of branch instructionREL
DIRDirect addressing moderel
ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingrr
EXTExtended addressing modeSP
ff Offset byte in indexed, 8-bit offset addressingX
H Half-carry flagZ
hh llHigh and low bytes of operand address in extended addressing#
I Interrupt mask∧
ii Immediate operand byte∨
IMMImmediate addressing mode⊕
INHInherent addressing mode( )
IXIndexed, no offset addressing mode–( )
IX1Indexed, 8-bit offset addressing mode←
IX2Indexed, 16-bit offset addressing mode?
MMemory location:
N Negative flag↕
n Any bit—
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
MC68HC(8)05PV8/A — Rev. 1.9
CPU and Instruction Set
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Technical Data