IC61C6416 Datasheet, PDF (9/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

256-Mbit GDDR3 DRAM [600MHz]
HYB18T256324F–16
HYB18T256324F–20
HYB18T256324F–22
1
Overview
1.1
Features
• Maximum clock frequency of 600 MHz
• Organization: 2048K x 32 x 4 banks
• 4096 rows and 512 columns (128 burst start
locations) per bank
• Differential clock inputs (CLK and CLK)
• CAS latencies of 5, 6 and 7
• Write latencies of 2, 3, 4
• Fixed burst sequence with length of 4.
• 4n prefetch
• Short RAS to CAS timing for Writes
• t_RAS Lockout support
• t_WR programmable for Writes with Auto-Precharge
• Data mask for write commands
• Single ended READ strobe (RDQS) per byte.
RDQS edge-aligned with READ data
• Single ended WRITE strobe (WDQS) per byte.
WDQS center-aligned with WRITE data
• DLL aligns RDQS and DQ transitions with Clock
• Programmable IO interface including on chip
termination (ODT)
• Autoprecharge option with concurrent
autoprecharge support
• 4K Refresh (32ms)
• Autorefresh and Self Refresh
• P-TBGA 144 package (11mm × 11mm)
• V_DD / V_DDQ Voltage (according to Table 1)
• Calibrated output drive. Active termination support.
Table 1 Key Timing and Power Supply Parameters
Speed Sort
–1.6
- 2.0
Power Supply
CAS latency = 7
CAS latency = 6
CAS latency = 5
Access Time
RDQS-DQ Skew
V_DD / V_DDQ
t_{CK7 min}
f_{CK7 max}
t_{CK6 min}
f_{CK6 max}
t_{CK5 min}
f_{CK5 max}
t_ACmin
t_ACmax
t_DQSQ
2.0 ± 100 mV
1.6
600
2.0
500
—
—
–0.4
0.4
0.225
2.0 ± 100 mV
2.0
500
2.0
500
—
—
–0.4
0.4
0.225
- 2.2
2.0 ± 100 mV
2.2
455
2.2
455
2.7
370
–0.45
0.45
0.25
Units
V
ns
MHz
ns
MHz
ns
MHz
ns
ns
ns
Data Sheet
9
Rev. 1.11, 04-2005
10292004-DOXT-FS0U