IC61C6416 Datasheet, PDF (37/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Table 23 WR Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
Unit Notes
–1.6
–2.0
–2.2
min max min max min max
CAS(a) to CAS(b) Command period
t_CCD
2
—2
Write Cycle Timing Parameters for Data and Data Strobe
—2
—
t_CK
1)
Write command to first WDQS latching t_DQSS
transition
WL - WL WL - WL WL - WL t_CK
0.25 +0.25 0.25 +0.25 0.25 +0.25
Data-in and Data Mask to WDQS Setup t_DS
Time
0.35 — 0.375 — 0.375 — ns ²⁾
Data-in and Data Mask to WDQS Hold t_DH
Time
0.35 — 0.375 — 0.375 — ns ²⁾
Data-in and DM input pulse width (each t_DIPW
input)
0.45 — 0.45 — 0.45 — t_CK
WDQS input low pulse width
t_DQSL
0.45 —
0.45 —
0.45 —
t_CK
3)
WDQS input high pulse width
t_DQSH
0.45 —
0.45 —
0.45 —
t_CK
3)
WDQS Write Preamble Time
t_WPRE 0.75 1.25 0.75 1.25 0.75 1.25 t_CK
WDQS Write Postamble Time
t_WPST
0.75 1.25 0.75 1.25 0.75 1.25 t_CK
Write to Read Command Delay
t_WTR
6.0 —
6.0 —
6.6 —
ns
2)4)
Write Recovery Time
t_WR
11.0 —
11.0 —
11.0 —
ns
2)4)
1) t_CCD is either for gapless consecutive writes or gapless consecutive reads
2) Timing parameters defined with Graphics DRAM terminations on.
3) t_DQSL. and t_DQSH apply for the Write preamble and postamble as well.
4) _tWTR and t_WR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQSx
signal
Data Sheet
37
Rev. 1.11, 04-2005
10292004-DOXT-FS0U