IC61C6416 Datasheet, PDF (25/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

3.3.2
Self Calibration for Driver and Termination
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#OM
!2&
./0
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
!DD
$1
Figure 7
T_+/
!2&!UTOREFRESH
$ONgT#ARE
+EEP/UTTIME
Termination update keep out time after Autorefresh command
Table 13 Termination update Keep Out time
Parameter
Symbol
Limit Values
Unit
–1.6
–2.0
–2.2
min max min max min max
Termination update Keep Out time
t_KO
10 — 10 — 10 — ns
Notes
To guarantee optimum driver impedance after power-up, the GDDR3 SGRAM needs 350 cycles after the clock is
applied and stable to calibrate the impedance upon power-up. The user can operate the part with fewer than 350
cycles, but optimal output impedance will not be guaranteed.
The GDDR3 Graphics RAM proceeds in the following manner for Self Calibration :
The PMOS device is calibrated against the external ZQ resistor value (Figure 8). First one PMOS leg is calibrated
against ZQ. The number of legs used for the terminators ( DQ and ADD/CMD) and the PMOS driver is represented
in Table 14. Next, one NMOS leg is calibrated against the already calibrated PMOS leg. The NMOS driver uses
6 NMOS legs.
Table 14 Number of Legs used for Terminator and Driver Self Calibration
Termination
Number of Legs Notes
CKE (at RES)
Terminator
ADD / CMD 0
ZQ/2
2
1
ZQ
1
EMRS[3:2]
DQ
00
Disabled
0
1
10
ZQ/4
4
11
ZQ/2
2
Driver
PMOS
ZQ/6
6
NMOS
ZQ/6
6
Note: EMRS[3:2] = 00 disables the ADD and CMD terminations as well.
Data Sheet
25
Rev. 1.11, 04-2005
10292004-DOXT-FS0U