English
Language : 

IC61C6416 Datasheet, PDF (47/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM
◁
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
T# (
T# ,
T# +
T( 0
#, +
#, +
2$ 1 3
0REAMB LE
T2 0 2%
T$ 1 3#+
0O STA MB LE
T2 0 34
$1FIRSTD ATAV A LID
$
$
$
$
$1 LASTD A TAV ALID
!LL$1 S C OLLE CTIVE LY
$
$
$
T! #
$
$
$
T$ 13 1
DATA T$ 13 1
T1(
T1 (3
VA LID
WINDOW
T, :
$
$
T(:
$O NgT# A RE
(I :.O TD RIVEN
BY$$ 2 )))3 ' 2! -
Figure 30 Basic Read Burst Timing
1. The GDDR3 SGRAM switches off the DQ terminations one cycle before data appears on the busand drives
the data bus HIGH.
2. The GDDR3 SGRAM drives the data bus HIGH one cycle after the last data driven on the bus before switching
the termination on again.
Table 25 READ Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
–1.6
–2.0
–2.2
min max min max min max
CAS (a) to CAS (b) Command period tCCD
2
—2
—2
—
Read to Write command delay
tRTW
tRTW(min)= (CL+4-WL)
Read Cycle Timing Parameters for Data and Data Strobe
Data Access Time from Clock
tAC
Read Preamble
tRPRE
Read Postamble
tRPST
Data-out high impedance time from CLK tHZ
Data-out low impedance time from CLK tLZ
RDQS edge to Clock edge skew
tDQSCK
RDQS edge to output data edge skew tDQSQ
Data hold skew factor
tQHS
Data output hold time from RDQS
tQH
Minimum clock half period
tHP
–0.4 0.4 –0.4 0.4 –0.45 0.45
0.75 1.25 0.75 1.25 0.75 1.25
0.75 1.25 0.75 1.25 0.75 1.25
tACmin
tACmin
–0.4
tACmax
tACmax
0.4
tACmin
tACmin
–0.4
tACmax
tACmax
0.4
tACmin
tACmin
–0.45
tACmax
tACmax
0.45
—
0.225 —
0.225 —
0.25
0
0.225 0
0.225 0
0.25
tHP–tQHS
0.45 —
tHP–tQHS
0.45 —
tHP–tQHS
0.45 —
Unit
tCK
tCK
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
Note
1
2
4
4
4
4
4
4
4
3
1. tCCD is either for gapless consecutive reads or gapless consecutive writes.
2. Please round up tRTW to the next integer of tCK.
3. tHP is the minimum of tCL and tCH
4. Timing parameters defined with controller terminations on.
Data Sheet
47
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
 ▷