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IC61C6416 Datasheet, PDF (35/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM
◁
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Table 21 ACT Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
–1.6
–2.0
–2.2
min max min max min max
Row Cycle Time
tRC
Row Active Time
tRAS
ACT(a) to ACT(b) Command
tRRD
period
37.2
24.0
8.0
—
8 x tREFI
—
37.2
24.0
8.0
—
8 x tREFI
—
39.6
26.2
8.8
—
8 x tREFI
—
Row to Column Delay Time for
Reads
tRCDRD
16.0 —
16.0 —
17.5 —
Row to Column Delay Time for tRCDWR
Writes
tRCDWR(min) = tRCDRD(min) - (WL + 1) x tCK(min)
Unit Notes
ns
ns
ns
ns
ns
3.7
Writes (WR)
3.7.1 Write Basic Information
#, +
#, +
#+ %
#3 
2!3 
#!3 
7% 
! ! !
#!
! !
! ! 
!
!0
"! "! 
"!
!0 ! UTO 0RE CHA RG E
#! # O LU MN! DD RE SS
"! " AN K!D D RE SS
$O NgT# A RE
Figure 19 Write Command
Write bursts are initiated with a WR command, as
shown in Figure 19. The column and bank addresses
are provided with the WR command, and Auto
Precharge is either enabled or disabled for that access.
The length of the burst initiated with a WR command is
always four. There is no interruption of WR bursts. The
two least significant address bits A0 and A1 are ’Don’t
Care’.
For WR commands with Autoprecharge the row being
accessed is precharged tWR/A after the completion of
the burst. If tRAS(min) is violated the begin of the internal
Autoprecharge will be performed one cycle after
tRAS(min) is met. tWR/A can be programmed in the Mode
Register. Choosing high values for tWR/A will prevent the
chip to delay the internal Autoprecharge in order to
meet tRAS(min).
During WR bursts data will be registered with the edges
of WDQS. The write latency can be programmed during
Extended Mode Register Set. The first valid data is
registered with the first valid rising edge of WDQS
following the WR command. The externally provided
WDQS must switch from HIGH to LOW at the beginning
of the preamble. There is also a postamble requirement
before the WDQS returns to HIGH. The WDQS signal
can only transition when data is applied at the chip input
and during pre- and postambles.
tDQSS is the time between WR command and first valid
rising edge of WDQS. Nominal case is when WDQS
edges are aligned with edges of external CLK.
Minimum and maximum values of tDQSS define early
and late WDQS operation. Any input data will be
ignored before the first valid rising WDQS transition.
tDQSL and tDQSH define the width of low and high phase
of WDQS. The sum of tDQSL and tDQSH has to be tCK.
Data Sheet
35
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
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