IC61C6416 Datasheet, PDF(51/80 Page) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

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IC61C6416 Datasheet, PDF (51/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

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HYB18T256324Fâ[16/20/22]

256-Mbit DDR SGRAM

Functional Description

3.8.3.3 Read followed by DTERDIS

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Figure 34 Read Command followed by DTERDIS

1. At least 3 NOPs are required between a READ command and a DTERDIS command in order to avoid

contention on the RDQS bus in a 2 rank system.

2. CAS Latency 5 is used as an example.

3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of

(BL/2 + 2 ) clocks.

4. The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command

corresponds to a Read command applied to the second Graphics DRAM in a 2 rank system. In this case,

RDQS would be driven by the second Graphics DRAM.

Data Sheet

51

Rev. 1.11, 04-2005

10292004-DOXT-FS0U

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