IC61C6416 Datasheet, PDF(23/80 Page) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

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IC61C6416 Datasheet, PDF (23/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

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HYB18T256324Fâ[16/20/22]

256-Mbit DDR SGRAM

Functional Description

3.2

Initialization

The HYB18T256324Fâ[16/20/22] must be powered up and initialized in a predefined manner. Operational

procedures other than those specified may result in undefined operation or permanent damage to the device.

The following sequence is highly recommended for Power-Up:

1. Apply power (VDD, VDDQ, VREF). Apply VDD before or at the same time as VDDQ, apply VDDQ before or at the same

time as VREF. Maintain RES=L and CS=H to ensure that all the DQ ouputs will be in HiZ state, all active

terminations off and the DLL off. All other pins may be undefined.

2. Maintain stable conditions for 200 Âµs minimum for the GDDR3 Graphics RAM to power up.

3. After clock is stable, set CKE to L. After tATS minimum set RES to high. On the rising edge of RES, the CKE

value is latched to determine the address and command bus termination value. If CKE is sampled LOW the

address termination value is set to ZQ / 2. If CKE is sampled HIGH, the address and command bus termination

is set to ZQ.

4. After tATH minimum, set CKE to high.

5. Wait a minimum of 350 cycles to calibrate and update the address and command termination impedances.

Issue DESELECT on the command bus during these 350 cycles.

6. Apply a PRECHARGE ALL command, followed by an Extended Mode Register command after tRP is met and

activate the DLL.

7. Issue an Mode Register Set command after tMRD is met to reset the DLL and define the operating parameters.

8. Wait 200 cycles of clock input to lock the DLL. No Read command can be applied during this time. Since the

impedance calibration is already completed, the DLL mimic circuitry can use the actual programmed driver

impedance value.

9. Issue a PRECHARGE ALL command or issue 4 single bank PRECHARGE commands, one to each of the 4

banks to place the chip in an idle state.

10. Issue two or more AUTO REFRESH commands to update the driver impedance.

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Power Up Sequence

MIN CY CLES

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MIN CY CLES

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Table 10 Reset Timing Parameters for â1.6, â2.0 and â2.2 speed sorts

Parameter

Symbol

Limit Values

Unit

â1.6

â2.0

â2.2

min max min max min max

RES to CKE setup time

RES to CKE hold time

tATS

10 â 10 â 10 â ns

tATH

10 â 10 â 10 â ns

Notes

Data Sheet

23

Rev. 1.11, 04-2005

10292004-DOXT-FS0U

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