IC61C6416 Datasheet, PDF (33/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.5.3 CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability
of the first bit of output data as shown on Figure 31. The latency can be set to 5 to 7 clocks as shown in Figure 15.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally
concident with clock edge n+m. Refer to Appendix, Figure 42, for values of operating frequencies at which each
CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
3.5.4 Write Latency
The WRITE latency, WL, is the delay, in clock cycles, between the registration of a WRITE command and the
availability of the first bit of input data as shown in Figure 21. WL can be set from 2 to 4 clocks depending on the
operating frequency. Setting the WRITE latency to 2 or 3 clocks will cause the device to enable the data input
receivers on all ACT commands.
3.5.5 Test mode
The normal operating mode is selected by issuing a Mode Register Set command with bit A7 set to zero and bits
A0-A6 and A8-A11 set to the desired value.
3.5.6 DLL Reset
The normal operating mode is selected by issuing a Mode Register Set command with bit A8 set to zero and bits
A0-A7 and A9-A11 set to the desired values. A DLL Reset is initiated by issuing a Mode Register Set command
with bit A8 set to one and bits A0-A7 and A9-A11 set to the desired values. The GDDR3 SGRAM returns
automatically in the normal mode of operations once the DLL reset is completed.
Data Sheet
33
Rev. 1.11, 04-2005
10292004-DOXT-FS0U