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IC61C6416 Datasheet, PDF (64/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.13
Power-Down
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Figure 51
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Power Down Command
Unlike SDR SDRAMs, the GDDR3 Graphics RAM
requires CKE to be active at all times an access is in
progress : From the issuing of a READ or WRITE
command until completion of the burst. For READs, a
burst completion is defined after the rising edge of the
Read Postamble. For Writes, a burst completion is
defined one clock after the rising edge of the Write
Postamble.
For Read with Autoprecharge and Write with
Autoprecharge, the internal Autoprecharge must be
completed before entering Power-Down.
Power-Down is entered when CKE is registered LOW
(no access can be in progress). If Power-Down occurs
when all banks are idle, this mode is referred to as
Precharge Power-Down; if Power-Down occurs when
there is a row active in any bank, this mode is referred
to as Active Power-Down. Entering power-down
deactivates the input and output buffers, excluding
CLK, CLK and CKE. For maximum power saving, the
user has the option of disabling the DLL prior to
entering power-down. In that case the DLL must be
enabled and reset after exiting power-down, and 200
cycles must occur before a READ command can be
issued.
In Power-Down mode, CKE low and a stable clock
signal must be maintained at the inputs of the GDDR3
Graphics RAM, all the other input signals are “Don’t
Care”. Power down duration is limited by the refresh
requirements of the device.
The Power-Down state is synchronously exited when
CKE is registered HIGH (along with a NOP or DESEL
command). A valid executable command may be
applied tXPN later.
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Figure 52 Power-Down Mode
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Table 30 Power Down Exit Timing Parameter for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
Unit
–1.6
–2.0
–2.2
min max min max min max
Precharge power-down exit timing
tXPN
5
—4
—4
—
tCK
Notes
Data Sheet
64
Rev. 1.11, 04-2005
10292004-DOXT-FS0U