IC61C6416 Datasheet, PDF(57/80 Page) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

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IC61C6416 Datasheet, PDF (57/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

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HYB18T256324Fâ[16/20/22]

256-Mbit DDR SGRAM

Functional Description

3.9.1 DTERDIS followed by READ

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Figure 41 DTERDIS Command followed by READ

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$1 S4 ERM INA TION S O FF

2$ 1 3. O TD RIV EN

1. At least 3 NOPs are required between a DTERDIS command and a READ command in order to avoid

contention on the RDQS bus in a 2 rank system.

2. CAS Latency 5 is used as an example.

3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of 4

clocks.

Data Sheet

57

Rev. 1.11, 04-2005

10292004-DOXT-FS0U

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