IC61C6416 Datasheet, PDF (21/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
14. During action WRITE/A an ACT or a PRE command
on another bank is allowed any time. A new WR or
WR/A command on another bank has to be
separated by at least one NOP from the ongoing
command. RD is not allowed before t_WTR is met.
RD/A is not allowed during an ongoing WRITE/A
action.
15. During action READ and READ/A an ACT or a PRE
command on another bank is allowed any time. A
new RD or RD/A command on another bank has to
be separated by at least one NOP from the ongoing
command. A WR or WR/A command on another
bank has to meet t_RTW.
2.4.3 Function Truth Table for CKE
Table 8 Function Truth Table II (CKE Table)
CKE CKE CURRENT STATE COMMAND
n-1 n
L
L
Power Down
X
Self Refresh
X
L
H
Power Down
DESEL or NOP
Self Refresh
DESEL or NOP
H
L
All Banks Idle
DESEL or NOP
Bank(s) Active
DESEL or NOP
All Banks Idle
Auto Refresh
ACTION
stay in Power Down
stay in Self Refresh
Exit Power Down
Exit Self Refresh ⁵
Entry Precharge Power Down
Entry Active Power Down
Entry Self Refresh
1. CKE_n is the logic step at clock edge n; CKE_n-1 was
the state of CKE at the previous clock edge.
2. Current state is the state of the GDDR3 Graphics
RAM immediatly prior to clock edge n.
3. COMMAND is the command registered at clock
edge n, and ACTION is a result of COMMAND.
4. All states and sequences not shown are illegal or
reserved.
5. DESEL or NOP commands should be issued on
any clock edges occuring during the t_XSR period. A
minimum of 200 clock cycles is required before
applying any other valid command.
Data Sheet
21
Rev. 1.11, 04-2005
10292004-DOXT-FS0U