IC61C6416 Datasheet, PDF(36/80 Page) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

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IC61C6416 Datasheet, PDF (36/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

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HYB18T256324Fâ[16/20/22]

256-Mbit DDR SGRAM

Functional Description

Back to back WR commands are possible and produce

a continuous flow of input data. There must be one

NOP cycle between two back to back WR commands.

Any WR burst may be followed by a subsequent RD

command. Figure 3.7.5 shows the timing requirements

for a WR followed by a RD. A WR may also be followed

by a PRE command to the same bank. tWR has to be

met as shown in Figure 3.7.8.

Setup and hold time for incoming DQs and DMs relative

to the WDQS edges are specified as tDS and tDH. DQ

and DM input pulse width for each input is defined as

tDIPW. The input data is masked if the corresponding DM

signal is high.

All timing parameters are defined with graphics DRAM

terminations on.

Table 22

WDQS

WDQS0

WDQS1

WDQS2

WDQS3

Mapping of WDQS and DM signals

Data mask signal

DM0

DM1

DM2

DM3

Controlled DQs

DQ0 - DQ7

DQ8 - DQ15

DQ16 - DQ23

DQ24 - DQ31

#,+

#, +

NOM IN AL7$ 1 3

7$ 1 3

$1

T$ 133

T7 02%

0REAM BLE

T$ 13

(

T$ 3 T$(

T$ 13 ,

T$ 1 3

(

T$ 3 T$(

T703 4

0OS TA MB LE

T$)0 7

$

$

$

$

$-X

EARLY 7 $ 1 3

7$ 1 3

LATE 7$ 1 3

7$ 1 3

$A TA MA S KE D

MINT$ 1 33

MA X T$ 13 3

T$ 3 T$ (

T$)0 7

$A TA M A SK E D

$O NgT# A RE

$- X 2 E PRE S EN TS O NE $ - LIN E

Figure 20 Basic Write Burst / DM Timing

Note: : WDQS can only transition when data is applied at the chip input and during pre- and postambles

Data Sheet

36

Rev. 1.11, 04-2005

10292004-DOXT-FS0U

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