IC61C6416 Datasheet, PDF (22/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

3
Functional Description
3.1
Clocks, CKE, Commands and Addresses
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
T_{# +}
T_{# (}
T_{# ,}
#, +
#, +
#-$ 
!$$ 2 
#+ %
6ALID
T_{)0 7}
6ALID
T₎₃ T₎₍
6ALID
$O N gT#A RE
Figure 4 Clock, CKE and Command/Address Timings
Setup and Hold Timing for CKE is equal to CMD and ADDR Setup and Hold Timing. The DLL ensures the
alignment of DQs and CLK. Therefore the preferred operation mode for high frequencies is DLL on. The DLL
frequency range is from 600 MHz down to 250 MHz.
Table 9 General Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
CAS Symbol
Limit Values
latency
–1.6
–2.0
min max min max
Clock
Clock Cycle Time
7
t_CK7
1.6
6
t_CK6
2.0
5
t_CK5
—
System frequency
7
f_CK7
300
6
f_CK6
300
5
f_CK5
—
Clock high level width
t_CH
0.45
Clock low-level width
t_CL
0.45
Command, CKE and Address Setup and Hold Times
3.3
3.3
—
600
500
—
0.55
0.55
2.0
2.0
—
250
250
—
0.45
0.45
4.0
4.0
—
500
500
—
0.55
0.55
Address/Command/CKE input setup t_IS
time
0.6 —
0.75 —
Address/Command/CKE input hold time t_IH
Address/Command/CKE input pulse
t_IPW
width
0.6 —
0.85 —
0.75 —
0.85 —
–2.2
min max
2.2 4.0
2.2 4.0
2.7 4.0
250 455
250 455
250 370
0.45 0.55
0.45 0.55
0.75 —
0.75 —
0.85 —
Unit
ns
ns
ns
MHz
MHz
MHz
t_CK
t_CK
ns
ns
t_CK
Data Sheet
22
Rev. 1.11, 04-2005
10292004-DOXT-FS0U