IC61C6416 Datasheet, PDF(55/80 Page) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

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IC61C6416 Datasheet, PDF (55/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

◁

HYB18T256324Fâ[16/20/22]

256-Mbit DDR SGRAM

Functional Description

3.9

Data Termination Disable (DTERDIS)

#, +

#, +

#+ %

#3

2!3

#!3

7%

The Data Termination Disable command is detected by

the device by snooping the bus for Read commands

when CS is high. The terminators are disabled starting

at CL - 1 clocks after the DTERDIS command is

detected and the duration is 4 clocks. The command

and address terminators are always enabled.

DTERDIS may only be applied to the GDDR3 Graphics

memory if it is not in the Power Down or in the Self

Refresh state.

The timing relationship between DTERDIS and other

commands is defined by the constraint to avoid

contention on the RDQS bus (i.e Read to DTERDIS

transistion) or the necessity to have a defined

termination on the data bus during Write (i.e. Write to

DTERDIS transition). ACT and PRE/PREALL may be

applied at any time before or after a DTERDIS

command.

! !!

!!

! !

!

"! "!

Figure 38

!0 ! UTO 0RE CHA RG E

$O NgT# A RE

Data Termination Disable Command

#, +

#, +

#O M

$4 $

.$

.$

.$

.$

.$

.$

.$

.$

.$

!DDR

$1

4E RM INATION

#! 3 LATE NCY

Figure 39 DTERDIS Timing

$A TA 4E RMINATIO NS A RE D ISA BLED

$4 $ $4 % 2$ )3

#O M# O MM AND

!D DR! D DRE S S" #

$O N gT#A RE

.$ ./ 0O R$ E SELEC T

Data Sheet

55

Rev. 1.11, 04-2005

10292004-DOXT-FS0U

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