IC61C6416 Datasheet, PDF (18/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
Table 5 Description of Commands
Command Description
PWDNEX
A CKE HIGH value sampled at a low to high transition of CLK is required to exit power down mode.
Once CKE is HIGH, the GDDR3 Graphics RAM must receive only NOP/DESEL commands until t_XPN
is satisfied. After t_XPN any command can be issued, but it has to comply with the state in which the
power down mode was entered.
DTERDIS
Data Termination Disable (Bus snooping for RD commands) : The Data Termination Disable
Command is detected by the device by snooping the bus for RD commands excluding CS. The
GDDR3 Graphics RAM will disable its Data terminators when a RD command is detected. The
terminators are disabled starting at CL - 1 clocks after the RD command is detected and the duration
is 4 clocks. In a two rank system, both DRAM devices will snoop the bus for RD commands to either
device and both will disable their terminators if a RD command is detected. The command and
address terminators are always enabled. See Figure 9 for an example of when the data terminators
are disabled during a RD command.
Table 6
Minimum delay from RD/A and WR/A to any other command (to another bank) with concurrent
Autoprecharge
From Command
To Command
Minimum delay to another bank
(with concurrent autoprecharge)
Note
WR/A
RD/A
RD or RD/A
WR or WR/A
PRE
ACT
RD or RD/A
WR or WR/A
PRE
ACT
(WL + 2) . t_CK + t_WTR
2 . t_CK
t_CK
t_CK
2 . t_CK
(CL + 4 - WL) . t_CK
t_CK
t_CK
Data Sheet
18
Rev. 1.11, 04-2005
10292004-DOXT-FS0U