IC61C6416 Datasheet, PDF (17/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
Table 5 Description of Commands
Command Description
PRE
The PRE command is used to deactivate the open row in a particular bank. The bank will be
available for a subsequent row access a specified time (t_RP) after the PRE command is issued.
Inputs BA0 and BA1 select the bank to be precharged. A8/AP is set to LOW. Once a bank has been
precharged, it is in the idle state and must be activated again prior to any RD or WR commands
being issued to that bank. A PRE command will be treated as a NOP if there is no open row in that
bank, or if the previously open row is already in the process of precharging.
PREALL
The PREALL command is used to deactivate all open rows in the memory device. The banks will
be available for a subsequent row access a specified time (t_RP) after the PREALL command is
issued. Once the banks have been precharged, they are in the idle state and must be activated prior
to any read or write commands being issued. The PREALL command will be treated as a NOP for
those banks where there is no open row, or if a previously open row is already in the process of
precharging. PREALL is issued by a PRE command with A8/AP set to HIGH.
AREF
The AREF is used during normal operation of the GDDR3 Graphics RAM to refresh the memory
content. The refresh addressing is generated by the internal refresh controller. This makes the
address bits “Don’t Care” during an AREF command. The HYB18T256324F–[16/20/22] requires
AREF cycles at an average periodic interval of t_REFI(max)=7.8µs. To improve efficiency a maximum
number of eight AREF commands can be posted to one memory device (with t_RFC from AREF to
AREF) as described in section Chapter 3.11. This means that the maximum absolute interval
between any AREF command is 8 x 7.8µs (62.4µs). This maximum absolute interval is to allow the
GDDR3 Graphics RAM output drivers and internal terminators to recalibrate, compensating for
voltage and temperature changes. All banks must be in the idle state before issuing the AREF
command. They will be simultaneously refreshed and return to the idle state after AREF is
completed. tRFC is the minimum required time between an AREF command and a following
ACT/AREF command.
SREFEN
The Self Refresh function can be used to retain data in the GDDR3 Graphics RAM even if the rest
of the system is powered down. When entering the self refresh mode by issuing the SREFEN
command, the GDDR3 Graphics RAM retains data without external clocking. The SREFEN
command is initiated like an AREF command except CKE is disabled (LOW). The DLL is
automatically disabled upon entering Self Refresh mode and automatically enabled and reset upon
exiting Self Refresh. (200 cycles must then occur before a RD command can be issued) The adress,
command and data terminators remain on input signals except CKE are “Don’t Care”. If two GDDR3
Graphics RAMs share the same cimmand and address bus, Self Refresh max be entered only for
the two devices at the sme time.
SREFEX
The SREFEX command is used to exit the self refresh mode. The DLL is automatically enabled and
resetted upon exiting. The procedure for exiting self refresh requires a sequence of commands. First
CLK and CLK must be stable prior to CKE going from LOW to HIGH. Once CKE is HIGH, the
GDDR3 Graphics RAM must receive only NOP/DESEL commands until t_XSNR is satisfied. This time
is required for the completion of any internal refresh in progress. A simple algorithm for meeting both
refresh, DLL requirements and output calibration is to apply NOPs for 200 cycles before applying
any other command to allow the DLL to lock and the output drivers to recalibrate.
PWDNEN
The PWDNEN command enables the power down mode. It is entered when CKE is set low together
with a NOP/DESEL. The CKE signal is sampled at the rising edge of the clock. Once the power
down mode is initiated, all of the receiver circuits except CLK and CKE are gated off to reduce power
consumption. The DLL remains active (unless disabled before with EMRS). All banks can be set to
idle state or stay active. During Power Down Mode, refresh operations cannot be performed;
therefore the refresh conditions of the chip have to be considered and if necessary Power Down
state has to be left to perform an Autorefresh cycle.
Data Sheet
17
Rev. 1.11, 04-2005
10292004-DOXT-FS0U