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IC61C6416 Datasheet, PDF (62/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM
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3.12
3.12.1
Self-Refresh
Self-Refresh Entry (SREFEN)
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Figure 47 Self Refresh Entry Command
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Figure 48 Self Refresh Entry
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
The Self-Refresh mode can be used to retain data in
the GDDR3 Graphics RAM even if the rest of the
system is powered down. When in the Self-Refresh
mode, the GDDR3 Graphics RAM retains data without
external clocking. The Self-Refresh command is
initiated like an Auto-Refresh command except CKE is
disabled (LOW). Self Refresh Entry is only possible if all
banks are precharged and tRP is met.
The GDDR3 Graphics RAM has a build-in timer to
accomodate Self-Refresh operation. The Self-Refresh
command is defined by having CS, RAS, CAS and CKE
held low with WE high at the rising edge of the clock.
Once the command is registered, CKE must be held
LOW to keep the device in Self-Refresh mode. When
the GDDR3 Graphics RAM has entered the Self-
Refresh mode, all external control signals, except CKE
are disabled. The address, command and data
terminators remain on. The DLL and the clock are
internally disabled to save power. The user may halt the
external clock while the device is in Self-Refresh mode
the next clock after Self-Refresh entry, however the
clock must be restarted before the device can exit Self-
Refresh operation.
32&
# LOC K
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MAY BE H ALTED
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O RLAS TO F0 2 % STO E AC HB AN K
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Data Sheet
62
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
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