IC61C6416 Datasheet, PDF (13/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
Table 3
Ball
RES
V_ref
V_DD, V_SS
V_DDQ, V_SSQ
NC, RFU
Ball description
Type Detailed Function
Input
Reset pin: The RES pin is a V_DDQ CMOS input. RES is not internally terminated. The
LOW to HIGH transition of the Reset signal is used to latch the CKE value during Power
On in order to set the value of the termination resistors of the address and command
inputs. When RES is LOW, all terminations are switched off. The LOW to HIGH transition
of the RES signal must occur at the beginning of the power up sequence in order to insure
functionnality.
Supply Voltage Reference: V_ref is the reference voltage input.
Supply Power Supply: Power and Ground for the internal logic.
Supply I/O Power Supply: Isolated Power and Ground for the output buffers to provide improved
noise immunity.
-
Please do not connect No Connect and Reserved for Future Use balls.
Data Sheet
13
Rev. 1.11, 04-2005
10292004-DOXT-FS0U