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IC61C6416 Datasheet, PDF (30/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.4.5 Low Power
When the Low Power extended mode register is set, the device enters a low power mode of operation. This mode
is not enabled for the HYB18T256324F–[16/20/22]. Setting this bit to HIGH will have no effect on the behavior of
the GDDR3 DRAM.
3.4.6 Vendor Code and Revision Identification
The Manufacturer Vendor Code is selected by issuing an Extended Mode Register Set command with bit A10 set
to 1 and bits A0-A9 and A11 set to the desired value. When the Vendor Code function is enabled the GDDR3
DRAM will provide the Infineon vendor code on DQ[3:0] and the revision identification on DQ[7:4]. The code will
be driven onto the DQ bus after tRIDon following the EMRS command that sets A10 to 1. The Vendor Code and
Revision ID will be driven on DQ[7:0] until a new EMRS command is issued with A10 set back to 0. After tRDoff
following the second EMRS command, the data bus is driven back to HIGH. This second EMRS command must
be issued before initiating any subsequent operation. Violating this requirement will result in unspecified operation.
Table 17 Revision ID and Vendor Code
Revision Identification
DQ[7:4]
0001
Infineon Vendor Code
DQ[3:0]
0010
Note: Please refer to Revision Release Note for Revision ID value











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Figure 13
Timing of Vendor Code and Revision ID generation on DQ[7:0]
%- 23 % X TE NDE D - OD E2 E GIS TER3 E T#O M MAN D
!D D!D D RE S S
.$ ./ 0OR$ E SELEC T
$O N gT#A RE
Table 18 Vendor Code and Revision ID Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
Unit Notes
–1.6
–2.0
–2.2
min max min max min max
EMRS to DQ on time
EMRS to DQ off time
tRIDon
—
20 —
20
—
20
ns
tRIDoff
—
20 —
20
—
20
ns
Data Sheet
30
Rev. 1.11, 04-2005
10292004-DOXT-FS0U