IC61C6416 Datasheet, PDF (26/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Figure 8 represents a simplified schematic of the calibration circuits. First, the strength control bits are adjusted
in such a way that the V_DDQ voltage is divided equaly between the PMOS device and the ZQ resistor. The best bit
pattern will cause the comparator to switch the PMOS Match signal output value. In a second step, the NFET is
calibrated against the already calibrated PFET. In the same manner, the best control bit combination will cause
the comparator to switch the NMOS Match signal output value.
Strength
Control [2:0]
VDDQ
PMOS
Calibration
VSSQ
VDDQ
NMOS
Calibration
VDDQ / 2
Match
ZQ
VDDQ / 2
Match
Strength
Control [2:0]
VSSQ
VSSQ
Figure 8 Self Calibration of PMOS and NMOS Legs
3.3.3 Dynamic Switching of DQ terminations
The GDDR3 Graphics RAM will disable its data terminators when a READ or DTERDIS command is detected. The
terminators are disabled starting at CL - 1 Clocks after the READ / DTERDIS command is detected and the
duration is 4 clocks. In a two rank system, both devices will snoop the bus for a READ / DTERDIS command to
either device and both will disable their terminators if a READ / DTERDIS command is detected. The address and
command terminators are always enabled.
Data Sheet
26
Rev. 1.11, 04-2005
10292004-DOXT-FS0U