IC61C6416 Datasheet, PDF (76/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
Table 43 Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Read Sym- Limit Values
latency bol
–1.6
–2.0
Unit Notes
–2.2
min max min max min max
Data-in and Data Mask to WDQS t_DH
Hold Time
0.35 —
0.375 —
0.375 —
ns
Data-in and DM input pulse width t_DIPW 0.45 —
(each input)
0.45 —
0.45 —
t_CK
DQS input low pulse width
t_DQSL 0.45 —
DQS input high pulse width
t_DQSH 0.45 —
DQS Write Preamble Time
t_WPRE 0.75 1.25
DQS Write Postamble Time
t_WPST 0.75 1.25
Write Recovery Time
t_WR 11.0 —
Read Cycle Timing Parameters for Data and Data Strobe
0.45
0.45
0.75
0.75
11.0
—
—
1.25
1.25
—
0.45 —
0.45 —
0.75 1.25
0.75 1.25
11.0 —
t_CK
t_CK
t_CK
t_CK
ns 3
Data Access Time from Clock
Read Preamble
Read Postamble
Data-out high impedance time from
CLK
t_AC
t_RPRE
t_RPST
t_HZ
–0.4
0.75
0.75
t_ACmin
0.4
1.25
1.25
t_ACmax
–0.4 0.4
–0.45 0.45 ns
0.75 1.25 0.75 1.25 t_CK
0.75 1.25 0.75 1.25 t_CK
t_ACmin t_ACmax t_ACmin t_ACmax ns
Data-out low impedance time from t_LZ
CLK
t_ACmin t_ACmax
t_ACmin t_ACmax t_ACmin t_ACmax ns
DQS edge to Clock edge skew
t_DQSCK –0.4 0.4
–0.4 0.4
–0.45 0.45 ns
DQS edge to output data edge skew t_DQSQ —
0.225 —
0.225 —
0.25 ns
Data hold skew factor
t_QHS 0
0.225 0
0.225 0
0.25 ns
Data output hold time from DQS t_QH t_HP–t_QHS
t_HP–t_QHS
t_HP–t_QHS
ns
Refresh/Power Down Timing
Refresh Period (4096 cycles)
Average periodic Auto Refresh
interval
t_REF —
32
t_REFI 7.8
— 32
— 32
ms
7.8
7.8
µs
Delay from AREF to next ACT/
AREF
t_RFC 54
—
54 —
54 —
ns
Self Refresh Exit time
t_XSC 200 —
Precharge Power Down Exit time t_XPN 5
—
Active Power Down Exit time
t _XARD 8
—
Other Timing Parameters
200 —
200 —
t_CK
4
—
4
—
t_CK
6
—
6
—
t_CK
RES to CKE setup timing
RES to CKE hold timing
Termination update Keep Out
timing
t_ATS 10
—
t_ATH 10
—
t_KO
10
—
10 —
10 —
ns
10 —
10 —
ns
10 —
10 —
ns
Rev. ID EMRS to DQ on timing
t_RIDon —
20
Rev. ID EMRS to DQ off timing
t_RIDoff —
20
— 20
— 20
ns
— 20
— 20
ns
1) t_HP is the lesser of t_CL minimum and t_CH minimum actually applied to the device CLK, CLK inputs
2) t_CCD is either for gapless consecutive reads or gapless consecutive writes.
3) t_WTR and t_WR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal.
4) Please round up t_RTW to the next integer of t_CK.
Data Sheet
76
Rev. 1.11, 04-2005
10292004-DOXT-FS0U