IC61C6416 Datasheet, PDF (74/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
Table 42 Operating Current Measurement Conditions
Symbol Parameter/Condition
I_DD2Q
Precharge Quiet Standby Current
CS is HIGH, all banks idle, CKE is HIGH, t_CK=min(t_CK), Address and other control inputs STABLE, Data
bus inputs are STABLE.
I_DD3P
Active Power-Down Standby Current
All banks active, CKE is LOW, Address and control inputs are STABLE; Data bus inputs are STABLE;
standard active power-down mode.
I_DD3N
I_DD4R
Active Standby Current
All banks active, CS is HIGH, CKE is HIGH, t_RC=max(t_RAS), t_CK=min(t_CK); Address and control inputs
are SWITCHING; Data bus inputs are SWITCHING; I_out = 0 mA.
Operating Current - Burst Read
All banks active; Continuous read bursts, CL = CL(min); tCK=min(t_CK); Address and control inputs are
SWITCHING; Data bus inputs are SWITCHING.
I_DD4W
Operating Current - Burst Write
All banks active; Continuous write bursts; t_CK=min(t_CK); Address and control inputs are SWITCHING;
Data bus inputs are SWITCHING.
I_DD5B
Burst Auto Refresh Current
Refresh command at t_RC=min(t_RFC); t_CK=min(t_CK); CKE is HIGH, CS is HIGH between all valid
commands; Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING.
I_DD5D
Distributed Auto Refresh Current
tCK=tCKmin; Refresh command every tREFI; CKE is HIGH, CS is HIGH between valid commands;
Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING.
I_DD6
Self Refresh Current
CKE ≤ max(V_IL), external clock off, CK and CK LOW; Address and control inputs are STABLE; Data
Bus inputs are STABLE.
I_DD7
Operating Bank Interleave Read Current
1. All banks interleaving with CL = CL(min); tRCD = tRCDRD(min); tRRD = tRRD(min); Iout=0mA;
Address and control inputs are STABLE during DESELECT; Data bus inputs are SWITCHING.
2: Timing pattern:
-1.6 (600 MHz, CL=7) : t_CK = 2.5ns, t_RCDRD = 7. t_CK; t_RRD = 4. t_CK; t_RC = 18. t_CK
Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D TBD TBD TBD
-2.0 (500 MHz, CL7) : t_CK = 2.0ns, t_RCDRD = 7. t_CK; t_RRD = 4. t_CK; t_RC = 18. t_CK
Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D
-2.2 (455 MHz, CL6) : t_CK = 2.2ns, t_RCDRD = 7. t_CK; t_RRD = 4. t_CK; t_RC = 18. t_CK
Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D
1. Data Bus consists of DQ, DM, WDQS
2. Definitions for IDD : LOW is defined as VIN = 0.4 x V_DDQ; HIGH is defined as V_IN = V_DDQ;
STABLE is defined as inputs are stable at a HIGH level.
SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and
control signals, and inputs changing 50% of each data transfer for DQ signals.
3. Legend : A=Activate, RA=Read with Autoprecharge, D=DESELECT
Data Sheet
74
Rev. 1.11, 04-2005
10292004-DOXT-FS0U