IC61C6416 Datasheet, PDF (67/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
4.3
DC & AC Logic Input Levels.
(0°C ≤ T_C ≤ +85°C, V_DD = +2.0 V ± 0.10 V, V_DDQ = +2.0 V ± 0.10 V, see Table 1)
Table 34 DC & AC Logic Input Levels
Parameter
Symbol
Input logic high voltage, DC
Input logic low voltage, DC
Input logic high voltage, AC
Input logic low voltage, AC
Input logic high, DC, RESET pin
Input logoc low, DC, RESET pin
V_IH(DC)
V_IL(DC)
V_{IH (AC)}
V_IL(AC)
V_IHR(DC)
V_ILR(DC)
Limit Values
min.
0.7 *V_DDQ + 0.15
—
0.7 *V_DDQ +0.4
—
0.8 *V_DDQ
-0.3
max.
—
0.7 *V_DDQ -0.15
—
0.7 *V_DDQ - 0.4
V_DDQ + 0.3
0.2 *V_DDQ
Unit Notes
V1
V1
V 2,3
V 2,3
V
V
1. The DC values define where the input slew rate requirements are imposed, and the input signal must not
violate these levels in order to maintain a valid level.
2. Input slew rate = 2 V/ns. If the input slew rate is less than 2 V/ns, input timing may be compromised. All slew
rates are measured between V_IL(DC) and V_IH(DC).
3. V_IH overshoot : V_IH(MAX) = V_DDQ+0.5 V for a pulse width ≤ 500ps and the pulse width cannot be greater than 1/3
of the cycle rate. V_IL undershoot: V_IL(MIN) = 0 V for a pulse width ≤ 500ps and the pulse width cannot be greater
than 1/3 of the cycle rate.
4.4
Differential Clock DC and AC Levels
(0°C ≤ T_C ≤ +85°C, V_DD = +2.0 V ± 0.10 V, V_DDQ = +2.0 V ± 0.10 V, see Table 1)
Table 35 Differential Clock DC and AC Input conditions
Parameter
Symbol Limit Values
min.
Clock Input Mid-Point Voltage, CLK and CLK V_MP(DC)
Clock Input Voltage Level, CLK and CLK V_IN(DC)
Clock DC Input Differential Voltage, CLK and V_ID(DC)
CLK
V_REF - 0.1
0.42
0.3
Clock AC Input Differential Voltage, CLK and V_ID(AC) 0.5
CLK
AC Differential Crossing Point Input Voltage V_IX(AC) V_REF - 0.15
max.
V_REF + 0.1
V_DDQ + 0.3
V_DDQ
V_DDQ + 0.5
V_REF + 0.15
Unit Note
s
V1
V1
V1
V 1, 2
V 1, 3
1. All voltages referenced to V_SS
2. V_ID is the magnitude of the difference between the input level on CLK and the input level on CLK.
3. The value of V_IX is expected to equal 0.7 x V_DDQ of the transmitting device and must track variations in the DC
level of the same.
Data Sheet
67
Rev. 1.11, 04-2005
10292004-DOXT-FS0U