IC61C6416 Datasheet, PDF(56/80 Page) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

IC61C6416 Datasheet, PDF (56/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

◁

!DD R

2$ 1 3

$1

#! 3LATE NC Y

HYB18T256324Fâ[16/20/22]

256-Mbit DDR SGRAM

Functional Description

#O M

.$

$4 $

.$

!DD R

#! 3LATE NC Y

2$ 1 3

$1

.$

.$

.$

.$

.$

.$

.$

.$

#O M

.$

.$

$4 $

.$

.$

.$

.$

.$

.$

.$

.$

!DD R

#! 3LATE NC Y

2$ 1 3

$1

Figure 40 DTERDIS followed by DTERDIS

#O M# O MMAN D

!DD R!D DRE SS" #

"# X "A N K# OLUM NAD D RE S SX

2$ 2 % ! $

$4 $$ 4 %2 $ )3

.$. / 0OR$ ES ELEC T

$X $A TAFRO M "#X

$O N gT#A RE

$1 S4 E RM IN ATIO NS O FF

2$ 1 3.O TD RIVE N

1. At least 1NOP is required between 2 DTERDIS commands. This correspond to a Read to Read transistion on

the other memory in a 2 rank system.

2. CAS Latency 5 is used as an example.

3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of (BL/2

+ 2 ) clocks

4. The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command

corresponds to a Read command applied to the second Graphics DRAM in a 2 rank system. In this case,

RDQS would be driven by the second Graphics DRAM.

Data Sheet

56

Rev. 1.11, 04-2005

10292004-DOXT-FS0U

▷