IC61C6416 Datasheet, PDF (15/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
2.3
Commands
2.3.1 Command Table
In the following table CKEn refers to the positive edge of CLK corresponding to the clock cycle when the command
is given to the Graphics SDRAM. CKEn-1 refers to the previous positive edge of CLK. For all command and
address inputs CKEn is implied.
All input states or sequences not shown are illegal or reserved.
Table 4 Command Overview
Operation
Code
Device Deselect
DESEL
CKE CKE CS
n-1 n
HHH
Data Terminator Disable DTERDIS H H H
No Operation
NOP
HHL
Mode Register Set
MRS
HHL
Extended Mode Register EMRS H H L
Set
Bank Activate
ACT
HHL
Read
RD
HHL
Read w/ Autoprecharge RD/A
HHL
Write
WR
HHL
Write w/ Autoprecharge WR/A
HHL
Precharge
PRE
HHL
Precharge All
PREALL H H L
Auto Refresh
AREF
HHL
Power Down Mode Entry PWDNEN H L H
L
Power Down Mode Exit PWDNEX L H X
Self Refresh Entry
SREFEN H L L
Self Refresh Exit
SREFEX L H X
RAS CAS WE BA0 BA1 A8 A2-7 Note
A9-11
L X XX X X X
1
XX L
HH H
H L HX X X X
1,9
H H HX X X X
L L L 0 0 OPCODE
L L L 1 0 OPCODE
L H H BA BA Row
1,2
Address
H L H BA BA L Col. 1,3
H L H BA BA H Col. 1,3
H L L BA BA L Col. 1,3
H L L BA BA H Col. 1,3
L H L BA BA L X
1
L H LXXHX
1
L L HX X X X
1,4
X X XX X X X
1,5
HH H
X X XX X X X
1,6
L L HX X X X
1,7
X X XX X X X
1,8
1. X represents “Don’t Care”.
2. BA0 and BA1 provide bank address, A0 - A11
provide the row address.
3. BA0 and BA1 provide bank address, A2- A7, A9
provide the column address, A8/AP controls Auto
Precharge.
4. Auto Refresh and Self Refresh Entry differ only by
the state of CKE
5. PWDNEN is selected by issuing a DESEL or NOP
at the first positive CLK edge following the HIGH to
LOW transition of CKE.
6. First possible valid command after t_XPN. During t_XPN
only NOP or DESEL commands are allowed.
7. Self Refresh is selected by issuing AREF at the first
positive CLK edge following the HIGH to LOW
transition of CKE.
8. First possible valid command after t_XSC. During t_XSC
only NOP or DESEL commands are allowed.
9. This command is invoked when a Read is issued on
another DRAM rank placed on the same command
bus. Cannot be in power-down or self-refresh state.
The Read command will cause the data termination
to be disabled. Refer to for timing.
Abbreviations:
BA:Bank Address
Col.:Column Address
Data Sheet
15
Rev. 1.11, 04-2005
10292004-DOXT-FS0U