IC61C6416 Datasheet, PDF (19/80 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH-SPEED CMOS STATIC RAM

HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
2.4
State Diagram and Truth Tables
2.4.1 State Diagram for One Activated Bank
The following diagram shows all possible states and transitions for one activated bank. The other three banks of
the Graphics SDRAM are assumed to be in idle state.
single bank
WR
ACTIVE
RD
ACT
PRE
WR/A
RD/A
PDEN PDEX
MRS
EMRS
AUTO
REFRESH
IDLE
PDEN
PDEX
SREN
SREX
active
POWER DOWN
precharge
SELF
REFRESH
all banks
Figure 3 State diagram for one bank
Note: MRS, EMRS, AUTO REFRESH, SELF REFRESH and precharge POWER DOWN are only allowed if all four
banks are idle.
Data Sheet
19
Rev. 1.11, 04-2005
10292004-DOXT-FS0U