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EP2C20F256C8N Datasheet, PDF (84/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1 | |||
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I/O Structure & Features
Figure 2â28. EP2C5 & EP2C8 I/O Banks Notes (1), (2)
I/O Bank 2 Also Supports
the SSTL-18 Class II,
HSTL-18 Class II, & HSTL-15
Class II I/O Standards
I/O Bank 2
I/O Bank 1
Also Supports the
3.3-V PCI & PCI-X
I/O Standards
I/O Bank 1
All I/O Banks Support
â 3.3-V LVTTL/LVCMOS
â 2.5-V LVTTL/LVCMOS
â 1.8-V LVTTL/LVCMOS
â 1.5-V LVCMOS
â LVDS
â RSDS
â mini-LVDS
â LVPECL (3)
â SSTL-2 Class I and II
â SSTL-18 Class I
â HSTL-18 Class I
â HSTL-15 Class I
â Differential SSTL-2 (4)
â Differential SSTL-18 (4)
â Differential HSTL-18 (5)
â Differential HSTL-15 (5)
Individual
Power Bus
I/O Bank 3
Also Supports the
3.3-V PCI & PCI-X
I/O Standards
I/O Bank 3
I/O Bank 4
I/O Bank 4 Also Supports
the SSTL-18 Class II,
HSTL-18 Class II, & HSTL-15
Class II I/O Standards
Notes to Figure 2â28:
(1) This is a top view of the silicon die.
(2) This is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations.
(3) The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
pins.
(4) The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock
pins.
(5) The differential 1.8-V and 1.5-V HSTL I/O standards are only supported on clock input pins and PLL output clock
pins.
2â58
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
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