EP2C20F256C8N Datasheet, PDF (390/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

PS Configuration
nCONFIG is low and during the beginning of configuration. Once the
optional bit to enable INIT_DONE is programmed into the device (during
the first frame of configuration data), the INIT_DONE pin goes low. When
initialization is complete, the INIT_DONE pin is released and pulled high.
This low-to-high transition signals that the FPGA has entered user mode.
If you do not use the INIT_DONE pin, the initialization period is complete
after the CONF_DONE signal transitions high and 299 clock cycles are sent
to the CLKUSR pin or after the time t_CF2UM (see Table 13–7) if the
Cyclone II device uses the internal oscillator.
After successful configuration, if you intend to synchronize the
initialization of multiple devices that are not in the same configuration
chain, your system must not pull the CONF_DONE signal low to delay
initialization. Instead, use the optional CLKUSR pin to synchronize the
initialization of multiple devices that are not in the same configuration
chain. Devices in the same configuration chain initialize together if their
CONF_DONE pins are tied together.
1 If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
User Mode
When initialization is complete, the FPGA enters user mode. In user
mode, the user I/O pins do not have weak pull-up resistors and function
as assigned in your design. Enhanced configuration devices and EPC2
devices drive DCLK low and DATA0 high (EPC1 devices drive the DCLK
pin low and tri-state the DATA pin) at the end of configuration.
When the FPGA is in user mode, pull the nCONFIG pin low to begin
reconfiguration. The nCONFIG pin should be low for at least 2 µs. When
nCONFIG transitions low, the Cyclone II device also pulls the nSTATUS
and CONF_DONE pins low and all I/O pins are tri-stated. Because
CONF_DONE transitions low, this activates the configuration device since
it will see its nCS pin transition low. Once nCONFIG returns to a logic high
level and nSTATUS is released by the FPGA, reconfiguration begins.
Error During Configuration
If an error occurs during configuration, the Cyclone II drives its nSTATUS
pin low, resetting itself internally. Since the nSTATUS pin is tied to OE,
the configuration device is also reset. If you turn on the Auto-restart
configuration after error option in the Quartus II software from the
General tab of the Device & Pin Options dialog box, the FPGA
automatically initiates reconfiguration if an error occurs. The Cyclone II
13–36
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007