EP2C20F256C8N Datasheet, PDF (428/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

IEEE Std. 1149.1 BST Architecture
f
This chapter discusses how to use the IEEE Std. 1149.1 BST circuitry in
Cyclone^™ II devices, including:
■ IEEE Std. 1149.1 BST architecture
■ IEEE Std. 1149.1 boundary-scan register
■ IEEE Std. 1149.1 BST operation control
■ I/O voltage support in JTAG chain
■ Using IEEE Std. 1149.1 BST circuitry
■ Disabling IEEE Std. 1149.1 BST circuitry
■ Guidelines for IEEE Std. 1149.1 boundary-scan testing
■ Boundary-Scan Description Language (BSDL) support
In addition to BST, you can use the IEEE Std. 1149.1 controller for
Cyclone II device in-circuit reconfiguration (ICR). However, this chapter
only discusses the BST feature of the IEEE Std. 1149.1 circuitry.
For information on configuring Cyclone II devices via the
IEEE Std. 1149.1 circuitry, see the Configuring Cyclone II Devices chapter in
Volume 1 of the Cyclone II Device Handbook.
IEEE Std. 1149.1
BST Architecture
A Cyclone II device operating in IEEE Std. 1149.1 BST mode uses four
required pins, TDI, TDO, TMS and TCK. The optional TRST pin is not
available in Cyclone II devices. TDI and TMS pins have weak internal
pull-up resistors while TCK has weak internal pull-down resistors. All
user I/O pins are tri-stated during JTAG configuration. Table 14–1
summarizes the functions of each of these pins.
Table 14–1. IEEE Std. 1149.1 Pin Descriptions
Pin
Description
Function
TDI
Test data input Serial input pin for instructions as well as test and programming data.
Signal applied to TDI is expected to change state at the falling edge
of TCK. Data is shifted in on the rising edge of TCK.
TDO
Test data output Serial data output pin for instructions as well as test and programming
data. Data is shifted out on the falling edge of TCK. The pin is tri-stated
if data is not being shifted out of the device.
TMS
Test mode select Input pin that provides the control signal to determine the transitions of
the TAP controller state machine. Transitions within the state machine
occur at the rising edge of TCK. Therefore, TMS must be set up before
the rising edge of TCK. TMS is evaluated on the rising edge of TCK.
During non-JTAG operation, TMS is recommended to be driven high.
TCK
Test clock input The clock input to the BST circuitry. Some operations occur at the
rising edge, while others occur at the falling edge. The clock input
waveform should have a 50% duty cycle.
14–2
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007