EP2C20F256C8N Datasheet, PDF (431/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone II Devices
to external device data via the PIN_IN signal, while the update registers
connect to external data through the PIN_OUT and PIN_OE signals. The
global control signals for the IEEE Std. 1149.1 BST registers (for example,
shift, clock, and update) are generated internally by the TAP controller.
The MODE signal is generated by a decode of the instruction register. The
data signal path for the boundary-scan register runs from the serial data
in (SDI) signal to the serial data out (SDO) signal. The scan register begins
at the TDI pin and ends at the TDO pin of the device.
Figure 14–4 shows the Cyclone II device’s user I/O boundary-scan cell.
Figure 14–4. Cyclone II Device's User I/O BSC with IEEE Std. 1149.1 BST Circuitry
Capture
Registers
Update
Registers
SDO
INJ
PIN_IN
0
0
DQ
DQ
1
1
INPUT
INPUT
From or
OEJ
To Device
I/O Cell
Circuitry
and/or
Logic
Array
OUTJ
0
0
DQ
DQ
1
0
1
OE
OE
1
V_CC
PIN_OE
0
DQ
DQ
1
OUTPUT
OUTPUT
0
PIN_OUT
Pin
1
Output
Buffer
SDI
SHIFT CLOCK
UPDATE HIGHZ MODE
Global
Signals
Altera Corporation
February 2007
14–5
Cyclone II Device Handbook, Volume 1