EP2C20F256C8N Datasheet, PDF (245/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II Memory Blocks
Figure 8–17. Cyclone II Read/Write Clock Mode
6 LAB Row
Clocks
6
data[ ]
DQ
ENA
rdaddress[ ]
DQ
ENA
Notes (1), (2)
Memory Block
256 ´ 16
Data In _{512 ´ 8}
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
Read Address
byteena[ ]
DQ
ENA
Data Out
Byte Enable
DQ
ENA
wraddress[ ]
rd_addressstall
wr_addressstall
rden (1)
wren
rdclocken
wrclocken
wrclock
rdclock
DQ
ENA
Write Address
Read Address
Clock Enable
Write Address
Clock Enable
DQ
ENA
Read Enable
Write Enable
DQ
ENA
Write
Pulse
Generator
To MultiTrack
Interconnect (2)
Notes to Figure 8–17:
(1) Violating the setup or hold time on the memory block address registers could corrupt memory contents. This applies
to both read and write operations.
(2) For more information about the MultiTract interconnect, refer to Cyclone II Device Family Data Sheet in volume 1 of
the Cyclone II Device Handbook.
Altera Corporation
February 2008
8–23
Cyclone II Device Handbook, Volume 1