EP2C20F256C8N Datasheet, PDF (228/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Overview
Figure 8–2. Cyclone II Byte Enable Functional Waveform
inclock
wren
address
an
a0
a1
a2
a0
data
XXXX
ABCD
a1
a2
XXXX
byteena
XX
10
01
11
XX
contents at a0
FFFF
ABFF
contents at a1
FFFF
FFCD
contents at a2
q (asynch)
FFFF
doutn
ABXX
XXCD
ABCD
ABCD
ABFF
FFCD
ABCD
f
Packed Mode Support
Cyclone II M4K memory blocks support packed mode. You can
implement two single-port memory blocks in a single block under the
following conditions:
■ Each of the two independent block sizes is less than or equal to half
of the M4K block size. The maximum data width for each
independent block is 18 bits wide.
■ Each of the single-port memory blocks is configured in single-clock
mode.
See “Single-Port Mode” on page 8–9 and “Single-Clock Mode” on
page 8–24 for more information.
Address Clock Enable
Cyclone II M4K memory blocks support address clock enables, which
holds the previous address value until needed. When the memory blocks
are configured in dual-port mode, each port has its own independent
address clock enable.
8–6
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008