EP2C20F256C8N Datasheet, PDF (197/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

PLLs in Cyclone II Devices
Figure 7–6. Phase Relationship between Cyclone II PLL Clocks in No
Compensation Mode
Phase Aligned
PLL inclk
PLL clock at the
register clock port (1)
External PLL clock outputs (2)
Notes to Figure 7–6:
(1) Internal clocks fed by the PLL are in phase with each other.
(2) The external clock outputs can lead or lag the PLL internal clocks.
Source-Synchronous Mode
If data and clock arrive at the same time at the input pins, they are
guaranteed to keep the same phase relationship at the clock and data
ports of any IOE input register. Figure 7–7 shows an example waveform
of the clock and data in this mode. This mode is recommended for
source-synchronous data transfer. Data and clock signals at the IOE
experience similar buffer delays as long as the same I/O standard is used.
Altera Corporation
February 2007
7–13
Cyclone II Device Handbook, Volume 1