EP2C20F256C8N Datasheet, PDF (285/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Selectable I/O Standards in Cyclone II Devices
Table 10–1. Cyclone II Supported I/O Standards and Constraints (Part 2 of 2)
I/O Standard
Differential HSTL-15 class I
or class II
Differential HSTL-18 class I
or class II
LVDS
RSDS and mini-LVDS (7)
LVPECL (8)
Type
Pseudo
differential (3)
Pseudo
differential (3)
Differential
Differential
Differential
V_CCIO Level
Top and
Bottom I/O
Pins
Side I/O Pins
Input
Output
CLK,
DQS
User I/O
Pins
CLK,
DQS
PLL_OUT
User I/O
Pins
(4) 1.5 V —
—
— _{v (6)}
—
1.5 V (4) v
—
v
—
—
(5)
(5)
(4) 1.8 V —
—
— _{v (6)}
—
1.8 V (4) v
—
v
—
—
(5)
(5)
2.5 V 2.5 V _v
v
v
v
v
(4) 2.5 V —
v
—
v
v
3.3 V/ (4)
—
—
—
2.5 V/
1.8 V/
v
v
1.5 V
Notes to Table 10–1:
(1) These pins support SSTL-18 class II and 1.8- and 1.5-V HSTL class II inputs.
(2) PCI-X does not meet the IV curve requirement at the linear region. PCI-clamp diode is not available on top and
bottom I/O pins.
(3) Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed
as inverted. Pseudo-differential HSTL and SSTL inputs treat differential inputs as two single-ended HSTL and
SSTL inputs and only decode one of them.
(4) This I/O standard is not supported on these I/O pins.
(5) This I/O standard is only supported on the dedicated clock pins.
(6) PLL_OUT does not support differential SSTL-18 class II and differential 1.8 and 1.5-V HSTL class II.
(7) mini-LVDS and RSDS are only supported on output pins.
(8) LVPECL is only supported on clock inputs, not DQS and dual-purpose clock pins.
3.3-V LVTTL (EIA/JEDEC Standard JESD8-B)
The 3.3-V LVTTL I/O standard is a general-purpose, single-ended
standard used for 3.3-V applications. The LVTTL standard defines the DC
interface parameters for digital circuits operating from a 3.0-/3.3-V
power supply and driving or being driven by LVTTL-compatible devices.
The LVTTL input standard specifies a wider input voltage range of
– 0.3 V ≤V_I ≤3.9 V. Altera recommends an input voltage range of
– 0.5 V ≤V_I ≤4.1 V.
Altera Corporation
February 2008
10–3
Cyclone II Device Handbook, Volume 1