EP2C20F256C8N Datasheet, PDF (443/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone II Devices
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When designing a board for JTAG configuration of Cyclone II devices, the
connections for the dedicated configuration pins need to be considered.
For more information on using the IEEE Std.1149.1 circuitry for device
configuration, see the Configuring Cyclone II Devices chapter in Volume 1
of the Cyclone II Device Handbook.
BST for
Configured
Devices
For a configured device, the input buffers are turned off by default for
I/O pins that are set as output only in the design file. Nevertheless,
executing the SAMPLE instruction will turn on the input buffers for the
output pins. You can set the Quartus II software to always enable the
input buffers on a configured device so it behaves the same as an
unconfigured device for boundary-scan testing, allowing sample
function on output pins in the design. This aspect can cause slight
increase in standby current because the unused input buffer is always on.
In the Quartus II software, do the following:
1. Choose Settings (Assignment menu).
2. Click Assembler.
3. Turn on Always Enable Input Buffers.
4. If you use the default setting with input disabled, you need to
convert the default BSDL file to the design-specific BSDL file using
the BSDLCustomizer script. For more information regarding BSDL
file, refer to “Boundary-Scan Description Language (BSDL)
Support”.
Altera Corporation
February 2007
14–17
Cyclone II Device Handbook, Volume 1