EP2C20F256C8N Datasheet, PDF (361/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Configuring Cyclone II Devices
Serial configuration devices provide a serial interface to access
configuration data. During device configuration, Cyclone II devices read
configuration data via the serial interface, decompress data if necessary,
and configure their SRAM cells. The FPGA controls the configuration
interface in the AS configuration scheme, while the external host (e.g., the
configuration device or microprocessor) controls the interface in the PS
configuration scheme.
1 The Cyclone II decompression feature is available when
configuring your Cyclone II device using AS mode.
Table 13–4 shows the MSEL pin settings when using the AS configuration
scheme.
Table 13–4. Cyclone II Configuration Schemes
Configuration Scheme
AS (20 MHz)
Fast AS (40 MHz) (1)
MSEL1
0
1
MSEL0
0
0
Note to Table 13–4:
(1) Only the EPCS16 and EPCS64 devices support a DCLK up to 40 MHz clock; other
EPCS devices support a DCLK up to 20 MHz. Refer to the Serial Configuration
Devices Data Sheet for more information.
Single Device AS Configuration
Serial configuration devices have a four-pin interface: serial clock input
(DCLK), serial data output (DATA), AS data input (ASDI), and an
active-low chip select (nCS). This four-pin interface connects to Cyclone II
device pins, as shown in Figure 13–3.
Altera Corporation
February 2007
13–7
Cyclone II Device Handbook, Volume 1