EP2C20F256C8N Datasheet, PDF (401/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Configuring Cyclone II Devices
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You can use a single configuration chain to configure Cyclone II devices
with other Altera devices. To ensure that all devices in the chain complete
configuration at the same time or that an error flagged by one device
initiates reconfiguration in all devices, connect all the Cyclone II device
CONF_DONE pins and connect all Cyclone II device nSTATUS pins
together.
For more information on configuring multiple Altera devices in the same
configuration chain, see the Configuring Mixed Altera FPGA Chains
chapter in the Configuration Handbook.
During PS configuration, the design must meet the setup and hold timing
parameters and maximum DCLK frequency. The enhanced configuration
and EPC2 devices are designed to meet these interface timing
specifications.
Figure 13–18 shows the timing waveform for the PS configuration scheme
using a configuration device.
Figure 13–18. Cyclone II PS Configuration Using a Configuration Device Timing Waveform
nINIT_CONF or
VCC/nCONFIG
t_POR
OE/nSTATUS
nCS/CONF_DONE
DCLK
t_OEZX
t_DSU t_CL
t_CH
t_DH
DATA
D₀ D₁ D2 D₃
D_n
t_CO
User I/O Tri-Stated with internal pull-up resistor
INIT_DONE
User Mode
t _CD2UM (1)
Note to Figure 13–18:
(1) Cyclone II devices enter user mode 299 clock cycles after CONF_DONE goes high. The initialization clock can come
from the Cyclone II internal oscillator or the CLKUSR pin.
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For timing information, refer to the Enhanced Configuration Devices
(EPC4, EPC8, and EPC16) Data Sheet or the Configuration Devices for
SRAM-based LUT Devices Data Sheet in the Configuration Handbook.
For more information on device configuration options and how to create
configuration files, see the Software Settings section in Volume 2 of the
Configuration Handbook.
Altera Corporation
February 2007
13–47
Cyclone II Device Handbook, Volume 1