EP2C20F256C8N Datasheet, PDF (225/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II Memory Blocks
Table 8–2. Number of M4K Blocks in Cyclone II Devices (Part 2 of 2)
Device
EP2C50
EP2C70
M4K Blocks
129
250
Total RAM Bits
594,432
1,152,000
Control Signals
Figure 8–1 shows how the register clocks, clears, and control signals are
implemented in the Cyclone II memory block.
The clock enable control signal controls the clock entering the entire
memory block, not just the input and output registers. The signal disables
the clock so that the memory block does not see any clock edges and will
not perform any operations.
Cyclone II devices do not support asynchronous clear signals to input
registers. Only output registers support asynchronous clears. There are
three ways to reset the registers in the M4K blocks: power up the device,
use the aclr signal for output register only, or assert the device-wide
reset signal using the DEV_CLRn option.
1 When applied to output registers, the asynchronous clear signal
clears the output registers and the effects are seen immediately.
Altera Corporation
February 2008
8–3
Cyclone II Device Handbook, Volume 1